
Circuit Diagrams and PWB Layouts
EN 97Q552.2L LA 10.
2011-Jul-15
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DC/DC
19110_034_110415.eps
110415
DC/DC
B03E B03E
2011-03-09
3
2010-12-23
2
3139 123 6521
SPB SSB TV550
2K11 4DDR BR SD
GND
VIN
HSPA
INH
SYNC
SW
VFB
A
SW
VIA
VIA
GND
VIN
HSPA
INH
SYNC
SW
VFB
A
SW
COM
OUTIN
COM
OUTIN
*
0402 Jumper
*
0402 Jumper
FOR 5000 SERIES ONLY
**
(*)
NOT FOR 5000 SERIES
(**)
*
7
35
1
6
ST1S10PH
7UD1-1
4
9
2
8
2
6
1
+1V1
RES
BC847BS(COL)
7U05-1
3UD0
68K
1%
3UD3
100K1%
S1D
6UD1
IUD1
IUD2
10
11
12
13
14 15
+12V
ST1S10PH
7UD0-2
IUD5
4n7
2UD7
IUD6
+2V5
10u
2UD2
4n7
2UE1
1%
3UD5
33K
5UD0
30R
IUD7
2UD1
10u
10u
2UD0
22u
2UE9
2U27
100n
RES
RES
16V22u
2UE6
+5V
+3V3
+12V
IU27
IUD3
IUD4
100n
2UE5
RES
100n
2U28
2UE3
22u
22u
2UE2
7U05-2
5
3
4
8
7
35
1
6
RES
BC847BS(COL)
7UD0-1
ST1S10PH
4
9
2
3UD4
1M0
IUD0
+3V3
1%
6UD0
SS36
33K
3UD1
IU28
FUD2
2UD8
10u
22u
2UD4
3u6
12
13
14 15
5UD1
7UD1-2
ST1S10PH
10
11
2UE8
22u 16V
10K
3U07
+5V
RES
3 2
+1V1
7UD2
LD1117DT25
1
2UE7
100n
120K
3UD2
220u 16V
2UE4
2UE0
10u
10u
2UD9
FUD3
+5V5-TUN
16V220u
2UD6
RES
1n0
2UD3
30R
5UD3
1
3 2
7UD3
LD1117DT33
3U06
10K
RES
2UD5
22u
3u6
5UD2
ENABLE-3V3-5V
ENABLE-3V3-5V
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